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Lattice Semiconductor
Figure 2-3. CIC Decimator Timing Diagrams
(a) Single-Channel: Inputs are sampled in every clock cycle:
clk
Functional Description
din
x(0)
x(1)
x(2)
x(3)
x(4)
x(5)
x(6)
x(7)
x( 8 )
x(9)
x(10)
x(11)
x(12)
x(13)
x(14)
x(15)
x(16)
x(17)
x(1 8 )
x(19)
inp v alid
do u t
y(0)
y(1)
y(2)
y(3)
y(4)
y(5)
y(6)
o u t v alid
Filter Latency + Rate Clock Cycles
Rate
Clock Cycles
Rate
Clock Cycles
Rate
Clock Cycles
Rate
Clock Cycles
Rate
Clock Cycles
Rate
Clock Cycles
(b) Single-Channel: Inputs are sampled in every two-clock cycle:
clk
din
x(0)
x(1)
x(2)
x(3)
x(4)
x(5)
x(6)
x(7)
x( 8 )
x(9)
inp v alid
do u t
y(0)
y(1)
y(2)
o u t v alid
Filter Latency + 2* Rate Clock Cycles
2* Rate Clock Cycles
2* Rate Clock Cycles
(c) Dual-Channel: Inputs are sampled in every clock cycle:
clk
din
x(0)
u (0)
x(1)
u (1)
x(2)
u (2)
x(3)
u (3)
x(4)
u (4)
x(5)
u (5)
x(6)
u (6)
x(7)
u (7)
x( 8 )
u ( 8 )
x(9)
i b start
inp v alid
do u t
y x (0)
y u (0)
y x (1)
y u (1)
y x (2)
y u (2)
o b start
o u t v alid
Filter Latency + 2* Rate Clock Cycles
Clock Cycles
2* Rate Clock Cycles
2* Rate Clock Cycles
2* Rate Clock Cycles
IPUG42_02.6, August 2010
14
Cascaded Integrator-Comb (CIC) Filter User’s Guide
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